1. Field of the Invention
The present invention relates to a technique for layout of a plurality of cells in a semiconductor memory such as an SRAM (static random access memory).
2. Description of the Background Art
FIGS. 14 and 15 are plan views of a layout structure of a high resistance load SRAM cell. This layout is disclosed in J. R. Pfiester etc., "A symmetric Vss cross-under bitcell technology for 64 Mb SRAMs", IEEE IEDM94, pp.623-626 (1994). As illustrated in FIG. 14, the layout structure comprises fields FLP, gate buried contacts GKP, first-level polysilicon interconnect layers 1GP for a gate, first buried contacts 1BP, and second-level polysilicon interconnect layers 2GP for a GND line. This provides word lines for access transistors ATrP1, ATrP2, gate layers for driver transistors DTrP1, DTrP2, and GND lines. Regions R .alpha. in which the fields FLP and the first-level polysilicon interconnect layers 1GP intersect have a low resistance because of implantation of impurities prior to the formation of the gates.
With reference to FIG. 15, the layout structure further comprises second buried contacts 2B, third-level polysilicon interconnect layers 3GP for a V.sub.CC line, contact holes CHP for contact with a bit line and a bit line, and aluminum layers ALP and ALP for the bit line and the bit line. This provides high-resistance and V.sub.CC lines (which one is produced to depend upon the presence/absence of impurity implantation), and the bit/bit line. The reference character CRP in FIGS. 14 and 15 designates the range of one cell.
The above described layout structure may implement a high resistance load SRAM circuit (FIG. 1) on a semiconductor substrate.
This layout has advantages to be described below because of its good symmetric property.
(1) Vertical or horizontal deviation of patterns significantly influences transistor characteristics. The above described layout, however, include symmetric patterns, permitting accordingly stable cell operation.
(2) The basically linear configuration of the patterns increases process stability since a pattern of a quadrilateral cross-sectional configuration is easy to produce but a pattern of a non-quadrilateral cross-sectional configuration is difficult to produce correctly. The above described layout includes fewer non-quadrilateral patterns.
(3) The longitudinal direction of the word lines 1GP (the gates of the access transistors) is the same as the longitudinal direction of the gates of the driver transistors. That is, both of the word lines 1GP and the gate layers for the driver transistors extend linearly in parallel in the direction of the word lines. This is advantageous in good controllability of the gate length during fabrication and in stable transistor characteristics. When a gate pattern is formed by the photolithographic process, a mask pattern has a rectangular shape, but a resist pattern influenced by light reflected from an underlying field pattern is inevitably rounded and has an unstable shape in actuality. However, the above described layout wherein the gate layers and the word lines 1GP extend linearly in the same direction in parallel to the underlying field pattern may reduce the influence of the rounded resist pattern.
The conventional layout structure illustrated in FIGS. 14 and 15, however, presents drawbacks to be described below.
First, it is necessary for the above-mentioned technique to form on the semiconductor substrate a total of four levels of interconnect layers: three levels of polysilicon interconnect layers and one level of metal interconnect layer, that is, the first-level, second-level, and third-level polysilicon interconnect layers (1GP, 2GP, 3GP), and the aluminum interconnect layers ALP, ALP. This inevitably requires a prolonged process and increased device costs.
The second drawback is that the third-level interconnect layers 3GP for the V.sub.CC line have a non-linear portion as shown in FIG. 15 in the above described layout including a number of linear patterns. The non-linear portion is an angular portion 3GR of the polysilicon interconnect layers 3GP which is enclosed by dotted circle of FIG. 15. Such a configuration creates a mismatch between a resist pattern RP2 and a layout pattern RP1, as schematically illustrated in the plan views of FIGS. 16A and 16B, for example. In the portion 3GR, the resist is not completely removed but remains during the photolithographic process as shown in FIG. 16B, resulting in the rounded configuration of the resist pattern RP2. This significantly decreases the controllability of the high resistance portions 3GP of FIG. 15. Specifically, for layout design, the value of a high resistance to be formed in a linearly extending high resistance portion formation portion 3GHR of the third-level polysilicon interconnect layers 3GP is previously predicted depending upon the number of sheets included in the area of the high resistance portion formation portion 3GHR. Unfortunately, if the rounded corners of the high resistance portion formation portion 3GHR shown in FIG. 16B cause the substantially decreased linear parts of the portion 3GHR, the resistance value of the high resistance portions 3GP is less than the predicted value, and the actual resistance value is not predictable during fabrication. The conventional layout structure still has such a problem to be solved.
The third drawback, as schematically shown in FIG. 17, is that the necessity to set a cover margin A for the second buried contact 2B, a clearance C between the third-level polysilicon interconnect layers 3GP, and a margin D for separation between the third-level polysilicon interconnect layer 3GP and the contact hole CHP decreases the width W of the polysilicon interconnect layer 3GP serving as a V.sub.CC interconnect line. This increases the resistance of the V.sub.CC interconnect line to develop a potential difference, failing to correctly supply a power supply potential V.sub.CC.
The fourth drawback is the increase in the resistance of a GND interconnect layer which should originally have a very low resistance. The gate lines and word lines are made of a composite material, for example, WSi/poly Si for the decrease in resistance thereof. It is a common practice to apply such composition to the GND interconnect layers for the above described purpose. The same is true for the conventional layout. In the conventional layout wherein the second-level interconnect layers 2GP for the GND line are formed above the first-level interconnect layers 1GP, this application produces a greater step of connection holes to increase the depth of the first buried contacts 1BP, resulting in an unignorable level of plug resistance, as will be described in greater detail later.